IBM Breaks the 1nm Barrier With Its Revolutionary "Nanostack" 3D Chip Architecture

Beyond the nanometer: IBM's atomic-scale leap

On June 25, 2026, IBM unveiled the world's first sub-1 nanometer chip technology — a 0.7-nanometer design built on an entirely new transistor architecture it calls "nanostack." The fingernail-sized chip packs nearly 100 billion transistors, almost twice the density of IBM's 2-nanometer chip from 2021, and is projected to deliver up to 50 percent higher computing performance or 70 percent greater energy efficiency compared to that prior generationnewsroom +1.

Building up, not out

The nanostack architecture is IBM's answer to a fundamental engineering crisis: transistors have been shrinking toward dimensions where quantum mechanics makes further conventional miniaturization unreliabletechnologyreview. Rather than pushing features laterally across a flat surface, IBM stacks two transistors vertically in a staggered arrangement — a technique related to a broader class of designs called complementary field-effect transistors, or CFETs. Intel, Samsung, TSMC, and the Belgian research lab Imec have all been pursuing CFET-style approaches, but IBM says its staggered layout simplifies wiring and allows different materials in each layer, independently tuning performance and power efficiency at the transistor levelarstechnica +1.

Each transistor consists of three nanosheets roughly 5 nanometers thick — about 15 rows of silicon atoms — spaced 9 nanometers apartarstechnica. The architecture also delivers a 40 percent improvement in SRAM scaling, the largest gain in roughly a decade and a significant advantage for AI workloads that depend on fast, dense memory accessnewsroom +1. "This achievement of 40 percent will eventually industrialize itself in AI workflows, which require higher bandwidth and high efficiency," IBM Research director Jay Gambetta saidarstechnica.

From lab bench to production line

IBM does not manufacture chips commercially; instead it licenses and partners its research breakthroughs to foundries. Its prior nanosheet architecture, also pioneered by IBM, is now used in every leading foundry's 2nm and 3nm processes and is currently being commercialized by Rapidus in Japanarstechnica. IBM declined to name prospective nanostack partners, but Huiming Bu, IBM's vice president of global semiconductor R&D, said production could begin within five years and that within a decade nanostack "will replace nanosheet as today's mainstream in leading foundries, whether it's CPUs or GPUs"arstechnica. IBM shares rose roughly 5 percent in premarket trading on the day of the announcementhothardware.

A decade more of Moore's Law

The milestone matters because analysts had long treated 1 nanometer as a practical endpoint for conventional scaling. Dan Hutcheson, vice chair of technology analysis firm TechInsights, called the advance "transformational," saying it "puts another 10, 15 years on the roadmap"technologyreview. IBM's research was validated through functional CMOS inverter operation at the VLSI 2026 symposium — confirming the chip performs real computation — and was conducted at IBM's Albany, New York research facility, which will soon house ASML's most advanced High NA EUV lithography toolnewsroom +1. IBM's roadmap now projects at least a decade of continued scaling in what it calls the "angstrom era," where chip dimensions approach the size of individual atomsnewsroom.